High speed digital logic circuits include transistors formed with thin gate oxide layers designed for high speed operation at low supply voltages. Many integrated circuits include digital logic circuits as well as interface circuitry designed to operate at higher voltages. Power BiCMOS circuit fabrication processes combine bipolar and complementary metal oxide semiconductor (CMOS) technologies to support low voltage, high speed digital logic circuits as well as higher voltage transistors to implement digital and analog input/output (IO) interface circuits, power management switches or the like. Certain approaches use laterally diffused MOS (LDMOS) or drain-extended MOS (DeMOS) transistors with drain structures capable of operating at higher voltages as compared to conventional symmetric MOS transistors. LDMOS transistors include a lightly doped lateral diffused drain region between the heavily doped drain contact and the transistor channel to conduct lateral current and form a depletion region to create a voltage drop between the drain contact and the transistor gate. The reduced drain voltage at the channel allows use of a thin gate oxide and a low gate voltage transistor can be used as a switch for high drain voltage applications. However, extending the lateral drift region to accommodate higher voltages increases the triode region on-state resistance RDSON and increases the device size, device cost and specific resistance Rsp. The specific resistance Rsp is the drain-to-source on-state resistance of the transistor in a given amount of area, and can be expressed as Rsp=RDSON*Area. In addition, the factor Q for transistor switching loss is related to the device input, output and reverse transfer capacitances, and low gate charge Qg, related to gate capacitance, and switching loss are important for high frequency operation. Split or stepped poly gates can be used to minimize main gate area for a reduced Qg, but this is only beneficial for a relatively high voltage rated device or a relatively long drift length. This approach also increases device size and cost and generally provides no significant device Rsp reduction. Moreover, addition of split gate structures over an extended drain increases the output or drain capacitance. Conventional LDMOS designs do not provide a complete solution for short channel devices with small pitch size for high voltage applications to reduce the specific resistance and still support efficient high frequency operation with low RDSON and Q.